A typical parallel processor utilizing a memory cell array is discussed illustratively by Duncan G. Elliott, W. Martin Snelgrove and Michael Stumm, "Computational Ram: A Memory-SIMD Hybrid and its Application to DSP" (CICC 30. 6. 1-30. 6. 4; May, 1992). This parallel processor is a semiconductor chip comprising a two-dimensional memory array and a large number of processing elements. The two-dimensional memory array has the advantage of allowing its numerous memory devices connected to word lines to be tapped simultaneously for reading of various data therefrom when any of those word lines are selected. The read data is supplied concurrently to a large number of processing elements. This makes it possible to carry out arithmetic processing at high speed where the numerous processing elements are run in parallel using a common instruction.
As outlined, the above type of parallel processor has been known for its ability to execute the same instruction simultaneously on a plurality of processors configured.